Field Effect Transistor, biasing
JFET, depletion and enhancement mode, MOSFET, FET amplifier
10 questions on each with explained answers
## Field Effect Transistor (FET)
**1. FET is a device?**
a) Bipolar
b) Unipolar
c) Current controlled
d) Voltage amplifier only
**Answer: b) Unipolar** [1]
**Explanation: FET conducts via majority carriers only, unlike BJT's both types. [1]
**2. FET input impedance range?**
a) Low ohms
b) Megaohms
c) Kiloohms
d) Infinite
**Answer: b) Megaohms** [1]
**Explanation:** Gate insulated from channel prevents DC current flow. [1]
**3. FET control mechanism?**
a) Current
b) Voltage
c) Power
d) Resistance
**Answer: b) Voltage** [2]
**Explanation:** Gate-source voltage modulates channel conductivity. [2]
**4. JFET noise compared to BJT?**
a) Higher
b) Lower
c) Equal
d) None
**Answer: b) Lower** [1]
**Explanation:** No junction injection reduces noise generation. [1]
**5. FET thermal stability?**
a) Poor like BJT
b) Better, no runaway
c) Worse
d) Equal
**Answer: b) Better, no runaway** [1]
**Explanation:** Majority carrier operation avoids thermal instability. [1]
**6. Radiation resistance of FET?**
a) Low
b) High
c) Same as BJT
d) Zero
**Answer: b) High** [1]
**Explanation:** Structure tolerates radiation better than BJTs. [1]
**7. FET gain type?**
a) High transconductance
b) Lower than BJT
c) Infinite
d) Zero
**Answer: b) Lower than BJT** [1]
**Explanation:** Lower gm limits voltage/current amplification. [1]
**8. JFET terminals?**
a) 2
b) 3: source, drain, gate
c) 4
d) 1
**Answer: b) 3: source, drain, gate** [3]
**Explanation:** Gate reverse-biased controls channel current. [3]
**9. Channel in JFET?**
a) Enhanced by gate
b) Depleted by gate voltage
c) Fixed
d) Absent
**Answer: b) Depleted by gate voltage** [3]
**Explanation:** Vgs widens depletion region, narrowing conduction path. [3]
**10. FET input resistance?**
a) Low
b) Very high
c) Medium
d) Variable only
**Answer: b) Very high** [3]
**Explanation:** Reverse-biased gate draws negligible current. [3]
## FET Biasing
**1. Purpose of FET biasing?**
a) Distortion increase
b) Set Q-point, reduce distortion
c) Maximum power
d) Minimum current
**Answer: b) Set Q-point, reduce distortion** [4]
**Explanation:** Establishes stable operating point for linear operation. [4]
**2. Fixed bias uses?**
a) Source resistor
b) Gate battery Vgg
c) Divider
d) Current source
**Answer: b) Gate battery Vgg** [5]
**Explanation:** Vgg reverse biases gate, Ig=0 through Rg. [5]
**3. Self bias advantage?**
a) Unstable
b) Stabilizes Id via Rs
c) High power
d) Complex
**Answer: b) Stabilizes Id via Rs** [5]
**Explanation:** Vgs = -Id Rs provides negative feedback. [5]
**4. Potential divider bias?**
a) Single resistor
b) Two gate resistors
c) Battery only
d) No resistors
**Answer: b) Two gate resistors** [5]
**Explanation:** Sets Vg independent of Id variations. [5]
**5. Current-source bias uses?**
a) BJT constant current
b) Low Vdd compensation
c) Fixed voltage
d) No source resistor
**Answer: a) BJT constant current** [5]
**Explanation:** BJT forces fixed Id through JFET. [5]
**6. Thermal runaway in FET?**
a) Common
b) Does not occur
c) Worse than BJT
d) Only n-channel
**Answer: b) Does not occur** [5]
**Explanation:** No minority carrier multiplication. [5]
**7. Biasing reduces?**
a) Dynamic range
b) Distortion, improves range
c) Gain
d) Impedance
**Answer: b) Distortion, improves range** [4]
**Explanation:** Fixed Q-point linearizes transfer curve. [4]
**8. Rg in fixed bias?**
a) Provides Vgs
b) AC signal path
c) DC block
d) Load
**Answer: b) AC signal path** [5]
**Explanation:** Zero DC drop allows coupling capacitor signals. [5]
**9. Source resistor feedback?**
a) Positive
b) Negative for stability
c) Zero
d) AC only
**Answer: b) Negative for stability** [5]
**Explanation:** Id increase raises Vgs negative, reducing Id. [5]
**10. Best bias for variation tolerance?**
a) Fixed
b) Self or divider
c) None
d) Current source only
**Answer: b) Self or divider** [5]
**Explanation:** Compensates parameter spreads unlike fixed bias. [5]
## JFET
**1. JFET channel type?**
a) Induced
b) Pre-existing, depleted
c) Enhanced
d) Absent
**Answer: b) Pre-existing, depleted** [1]
**Explanation:** N-channel or P-channel doped initially. [1]
**2. JFET pinch-off voltage?**
a) Vgs=0
b) Vgs where Id=0
c) Vds sat
d) Vdd
**Answer: b) Vgs where Id=0** [1]
**Explanation:** Maximum reverse Vgs closes channel. [1]
**3. JFET operation region?**
a) Saturation only
b) Ohmic and saturation
c) Cutoff always
d) Linear only
**Answer: b) Ohmic and saturation** [1]
**Explanation:** Vds low: resistor; high: constant Id. [1]
**4. Gate current in JFET?**
a) High
b) Negligible reverse leakage
c) Forward
d) Equal Id
**Answer: b) Negligible reverse leakage** [1]
**Explanation:** Reverse-biased PN junction. [1]
**5. JFET transconductance?**
a) High like BJT
b) Lower
c) Infinite
d) Zero
**Answer: b) Lower** [1]
**Explanation:** gm = dId/dVgs smaller than BJT hfe. [1]
**6. N-channel JFET Vgs?**
a) Positive
b) Negative or zero
c) AC only
d) Positive high
**Answer: b) Negative or zero** [3]
**Explanation:** Depletes n-channel with negative gate. [3]
**7. JFET application?**
a) Low impedance only
b) High Z amplifiers, RF
c) Power only
d) Digital
**Answer: b) High Z amplifiers, RF** [1]
**Explanation:** Suits buffer, preamp stages. [1]
**8. Transfer curve JFET?**
a) Linear
b) Parabolic Id vs Vgs
c) Exponential
d) Step
**Answer: b) Parabolic Id vs Vgs** [3]
**Explanation:** Channel width squared effect. [3]
**9. Maximum Id at?**
a) Vgs= Vp
b) Vgs=0
c) Vgs positive
d) Vds=0
**Answer: b) Vgs=0** [1]
**Explanation:** Full channel width. [1]
**10. JFET symbol gate?**
a) Arrow out
b) Arrow in for N-ch
c) No arrow
d) Circle
**Answer: b) Arrow in for N-ch** [3]
**Explanation:** Indicates channel type convention. [3]
## Depletion and Enhancement Mode
**1. Depletion MOSFET channel?**
a) Absent initially
b) Pre-doped, conducts Vgs=0
c) Induced only
d) N-type only
**Answer: b) Pre-doped, conducts Vgs=0** [6]
**Explanation:** Like JFET, channel exists without gate voltage. [6]
**2. Enhancement MOSFET channel?**
a) Pre-exists
b) Formed by positive Vgs
c) Depleted
d) Fixed
**Answer: b) Formed by positive Vgs** [6]
**Explanation:** Vgs exceeds threshold induces carriers. [6]
**3. Depletion mode Vgs range?**
a) Positive only
b) Both positive/negative
c) Zero only
d) Negative only
**Answer: b) Both positive/negative** [6]
**Explanation:** Can enhance or deplete channel. [6]
**4. Enhancement Vgs for conduction?**
a) Zero
b) Above Vth
c) Below Vth
d) Negative
**Answer: b) Above Vth** [7]
**Explanation:** No channel until threshold reached. [7]
**5. Depletion gate voltage effect?**
a) Increases conduction
b) Decreases conductivity
c) No effect
d) Off only
**Answer: b) Decreases conductivity** [7]
**Explanation:** Positive/negative Vgs widens depletion. [7]
**6. Enhancement off-state?**
a) Vgs=0
b) Vgs high
c) Vds high
d) Always on
**Answer: a) Vgs=0** [6]
**Explanation:** No inversion layer forms. [6]
**7. MOSFET types work modes?**
a) Depletion both modes
b) Enhancement depletion only
c) Both one mode
d) None
**Answer: a) Depletion both modes** [6]
**Explanation:** Dual operation capability. [6]
**8. Channel construction in enhancement?**
a) Doped
b) Gate voltage induced
c) Permanent
d) External
**Answer: b) Gate voltage induced** [7]
**Explanation:** Inversion layer under gate oxide. [7]
**9. Depletion Id at Vgs=0?**
a) Zero
b) Maximum
c) Minimum
d) Negative
**Answer: b) Maximum** [6]
**Explanation:** Full channel available. [6]
**10. Threshold voltage enhancement?**
a) Negative
b) Positive for N-ch
c) Zero
d) Variable only
**Answer: b) Positive for N-ch** [2]
**Explanation:** Required to bend bands for inversion. [2]
## MOSFET
**1. MOSFET full form?**
a) Metal Oxide Semiconductor FET
b) Junction FET
c) Bipolar FET
d) Current FET
**Answer: a) Metal Oxide Semiconductor FET** [2]
**Explanation:** Gate oxide insulates control terminal. [2]
**2. MOSFET regions?**
a) 2
b) 3: cutoff, triode, saturation
c) 4
d) 1
**Answer: b) 3: cutoff, triode, saturation** [8]
**Explanation:** Analogous to BJT but voltage controlled. [8]
**3. N-MOSFET Vds negative?**
a) Active
b) Inactive/ohmic
c) Saturation
d) Cutoff
**Answer: b) Inactive/ohmic** [8]
**Explanation:** Reverse polarity blocks conduction. [8]
**4. Linear resistor MOSFET region?**
a) Saturation
b) Triode
c) Cutoff
d) All
**Answer: b) Triode** [8]
**Explanation:** Vds << Vgs-Vth acts as resistor. [8]
**5. Linear amplifier region?**
a) Triode
b) Saturation
c) Cutoff
d) Ohmic
**Answer: b) Saturation** [8]
**Explanation:** Constant Id for voltage gain. [8]
**6. MOSFET input impedance?**
a) Low
b) Very high
c) Medium
d) Zero
**Answer: b) Very high** [2]
**Explanation:** Insulated gate draws no current. [2]
**7. Temperature coefficient MOSFET?**
a) Negative
b) Positive
c) Zero
d) Variable
**Answer: b) Positive** [8]
**Explanation:** Reduces thermal runaway risk. [8]
**8. Minority carriers in MOSFET?**
a) Present
b) Absent
c) Dominant
d) Equal
**Answer: b) Absent** [8]
**Explanation:** Unipolar majority carrier device. [8]
**9. I-V MOSFET vs BJT?**
a) Linear both
b) Quadratic Vgs MOSFET
c) Exponential both
d) Same
**Answer: b) Quadratic Vgs MOSFET** [8]
**Explanation:** Id ∝ (Vgs-Vth)^2 in saturation. [8]
**10. MOSFET on-state?**
a) High resistance
b) Low resistance
c) Infinite
d) Zero current
**Answer: b) Low resistance** [8]
**Explanation:** Fully enhanced channel. [8]
## FET Amplifier
**1. Common source like?**
a) Common emitter
b) High Z in, voltage gain
c) Buffer
d) Current amp
**Answer: b) High Z in, voltage gain** [9]
**Explanation:** Most common FET amplifier type. [9]
**2. FET amp advantage?**
a) Low Z
b) High input Z, low noise
c) High power
d) Complex
**Answer: b) High input Z, low noise** [9]
**Explanation:** Minimal loading, IC compatible. [9]
**3. Common drain configuration?**
a) Voltage gain high
b) Unity gain buffer
c) Phase invert
d) Low Z out
**Answer: b) Unity gain buffer** [9]
**Explanation:** Emitter follower equivalent. [9]
**4. Input capacitance CS amp?**
a) Cgs only
b) Cgs + Cgd(1+Av) Miller
c) Zero
d) Infinite
**Answer: b) Cgs + Cgd(1+Av) Miller** [9]
**Explanation:** Feedback capacitance multiplied. [9]
**5. Common gate use?**
a) High freq, impedance match
b) Voltage amp
c) Buffer
d) Low Z in
**Answer: a) High freq, impedance match** [9]
**Explanation:** Low input Z to high output Z. [9]
**6. CS output phase?**
a) In-phase
b) 180° shift
c) 90°
d) None
**Answer: b) 180° shift** [9]
**Explanation:** Like CE, Vd falls as Vg rises. [9]
**7. FET amp power consumption?**
a) High gate current
b) Low, no gate DC path
c) Equal BJT
d) Maximum
**Answer: b) Low, no gate DC path** [9]
**Explanation:** Ig ≈ 0 ideally. [9]
**8. Cascode advantage?**
a) Low gain
b) High freq, Miller reduction
c) Buffer
d) Simple
**Answer: b) High freq, Miller reduction** [9]
**Explanation:** Common gate isolates feedback. [9]
**9. Rout CS MOSFET amp?**
a) Low
b) ro || RD
c) Infinite
d) Zero
**Answer: b) ro || RD** [9]
**Explanation:** Drain degeneration none assumed. [9]
**10. Ideal max voltage common drain?**
a) 0
b) 1
c) 0.5
d) 2
**Answer: b) 1** [10]
**Explanation:** Voltage follower gain approaches unity. [10]
